1. Field of the Invention
The present invention generally relates to integrated circuit fabrication techniques and, particularly, to a maskless process for forming contact regions in an integrated circuit substrate, particularly useful for high density, complementary metal-oxide-semiconductor (CMOS) circuits.
2. Description of the Related Art
Very large scale integration (VLSI) in integrated circuit technology has resulted in semiconductor chips in which the geometry of individual components is continuously scaled downward in order to provide more complex integrated circuits, to improve performance, and to conserve chip area for better manufacturing yield, using substantially the same die sizes. The basic objective in scaling is to preserve the original device characteristics in miniaturized geometry.
In order to create the complex, three-dimensional structure of an integrated circuit, the execution of a large number of individual and complex interactive operations is required. The photolithographic fabrication process requires repeated transfers of an image from a photosensitive mask, "photoresist," to a semiconductor wafer. If the device is to operate in accordance with the circuit design, it is critical that each layer be correctly aligned with previously formed layers. The larger the number of layers and interconnections the more masks used, and the more critical the alignment factor.
Fabrication technology commonly is referred to in terms relating to aspects of the dimensions of certain regions of a particular circuit. For example, in circuits which use field effect transistors (FET) having a "channel region," the process used to fabricate the chip often is referred to by the channel length, i.e. "a 1.5 micron process" or a "submicron process." As dimensions shrink, photolithographic techniques encounter significant problems. Primary problems in getting submicron resolution with optical-imaging equipment are standingwave patterns generated in the photoresist, the change in focus of projected images, and the light scattering and lateral exposure that causes changes in the width of individual regions of the structure.
For each individual level, the minimum line width of a feature and the minimum separation between these features on a fully processed wafer is defined by the design rules. These dimensions are a function of the minimum dimensions on a mask that can be resolved in the lithography and the change that the feature undergoes during the specific steps in the process that define and follow the definition of the feature. For example, a local oxidation process to form an insulating field oxide region causes the space between active regions to change. Hence, the final separation between these features in a silicon substrate will be different from that on the mask. As another example, lateral diffusion of impurities due to temperature changes and the lateral extent of the junction depletion layers under applied voltages also govern the minimum separation between devices on a given level. The design rules governing the minimum separation between features must take these types of effects into account.
An important alignment factor of the design rules is commonly referred to as "overlay tolerance" or "overlap." Overlap is again a function of the lithographic tool and its alignment accuracy. A typical alignment accuracy of current lithographic stepper machines is, for practical purposes, about 0.7 micron. The design rules must include a tolerance for misalignment of features in order to overcome the limitations of the lithographic process to insure, for example, that an interconnect layer actually contacts the proper subjacent transistor regions in accordance with the circuit design.
FIG. 1 depicts a tolerance region of particular concern, viz., the alignment of a contact window to an active region of the semiconductor substrate; e.g., a FET source/drain region adjacent to a field oxide, (shown in overlaying different planar aspects). The overlap tolerance is defined as "x" where "y" is the effective overlap dimension which determines contact breakdown voltage. As device density increases, the accurate alignment of contact windows becomes more critical to the layout and, at the same time, more difficult.